As integrated circuits (ICs) continue to decrease in size as a consequence of market demand, fin field-effect transistors (finFETs) are used extensively for their relatively higher drive current and ability to prevent short-channel effects. However, use of finFETs in smaller technology has led to an increased susceptibility of failure for finFETs from ESD because of their relatively small channel width. For the ESD protection, the current shunting capabilities of finFETs are limited by the constraints of on-chip area. The smaller channel width leads to an increased current density during an ESD event resulting in breakdown of the dielectric gate oxide between the active area and the gate. As a result, finFETs may experience complete failure because the breakdown may result in a short between the gate and the active area. Further, an increasing number of specific applications such as in the automotive field need high voltage (HV) devices. However, HV devices are difficult to build on finFET or VFET technology.
A need therefore exists for methodology enabling forming HV ESD structures in a VFET process to address the scaling and design challenges of ESD protection in deeply scaled technologies.